The processes for a mobile communication system relating to the present invention will briefly be described with reference to FIG. 1. FIG. 1 shows a user 102, a communication terminal 101 and a base station 100. The user 102 accesses the base station 100 using the communication terminal 101 and thus receives various services. The communication with other communication terminals is also performed through the base station 100. The communication process between the communication terminal and the base station, therefor, constitutes the essential part of the communication.
The communication terminal 101 includes a user interface/system controller 109 having the user interface function and the system control function, a communication protocol processing unit 110 having the communication protocol processing function, a code/decode processing unit 111 having the speech coding/decoding function, the channel coding/decoding function, the modulation/demodulation function, etc., and an AFE/RF circuit section 105 having an analog front end (AFE) and an RF circuit. The communication terminal 101 is connected with a microphone (MIC) 103 and a speaker (SPK) 104. The base station 100 includes a system controller 112 having the system control function, a communication protocol processing unit 113 having the communication protocol processing function, a channel coding/decoding function, the modulate/demodulate function, etc., and an AFE/RF circuit section 106 having an analog front end (AFE) and an RF circuit.
The communication terminal 101 exchanges information with the base station 100 generally in one of two modes: Audio or the like user data are exchanged, or control data for system management are exchanged.
Audio data are exchanged in the following manner. The audio data input from the microphone (MIC) 103 are converted into digital data and compressed by the speech encoding process in the code/decode processing unit 111. The compressed audio data have added thereto error correction information by the channel encoding process in the code/decode processing unit 111, and then modulated by the modulation process in the code/decode processing unit 111. These processes are performed in a digital area. The modulated digital voice is converted into analog data in the analog front end (AFE) of the AFE/RF circuit section 1605, and transmitted from an antenna 107 over a radio-frequency wave by the RF circuit of the AFE/RF circuit section 105. This radio wave is received by an antenna 108 of the base station 100 and temporarily demodulated. This radio wave is modulated again on the frequency (in the case of frequency multiplexing) assigned to the other party of communication, and retransmitted from the base station to the other party in a timing of time slots (in the case of time division multiplexing) assigned to the other party.
Now, the exchange of the control data for system management will be explained. The communication protocol processing unit 110 in the communication terminal 101 and the communication protocol processing unit 113 in the base station 100 exchange data with each other. A virtual logic connection is established between these two functions. This virtual logic connection is realized by a physical connection described below. In the case where the base station 100 issues some instruction to the communication terminal, the process is performed as follows. The instruction data according to a predetermined protocol is encoded for the communication path and modulated in the code/decode processing unit 114. The resulting data are converted into analog data in the analog front end (AFE) of the AFE/RF circuit section 106, and transmitted from the RF circuit over a radio wave by way of the antenna 108. This radio wave is received by the antenna 107 of the communication terminal 101 and converted into baseband digital data through the RF circuit of the RF circuit 105 and the analog front end (AFE). The digital data are further demodulated and decoded for the communication path by the code/decode processing unit 111 and delivered to the communication protocol processing unit 110.
The two manners in which the communication terminal 101 exchanges data with the base station 100 and the related processes are described above. The processes related to these operations are generally divided into two types. The speech coding/encoding process, the channel coding/decoding process and the modulation/demodulation process are classified as a digital signal process which is suitably realized by an exclusive hardware or a programmable DSP (digital signal processor). The communication protocol process, on the other hand, is so complicated that it is suitably realized by software using a high-level language such as the C language.
In view of these facts, a method has recently been proposed in which the speech coding/encoding process, the channel coding/decoding process and the modulate/demodulate process are performed by a DSP, and the communication protocol process is performed by a CPU (general-purpose microprocessor), among the baseband processes of the mobile communication terminal (“Latest Information on GSM/Systems, Terminals and Services”, Seminar materials, Japan Industrial Technological Center, May 18 to 19, 1965, and “Development Trend of GSM Telephone Terminal Devices”, pp. 118–130, Japan Phillips).
Explanation will be made about an example of a mobile communication terminal including a DSP and a CPU studied by the inventor according to the above-mentioned well-known examples. The example explained below is not an exact replica of any well-known examples. This mobile communication terminal is intended for the GSM (global system for mobile communications) constituting a specification of a digital cellular telephone in Europe. The mobile communication terminal shown in FIG. 2 includes a DSP chip 223, a DSP RAM (random access memory) 200, a DSP ROM (read-only memory) 201, a CPU chip 227, a baseband analog front end (AFE) 202, a RF modem 210, a power amplifier (PA) 212, an antenna 213, a duplexer 214, a low-noise amplifier (LNA) 215, a microphone 208, an amplifier Amp, a speaker 209, a drive circuit Dri, a frequency synthesizer 216, a system timing circuit 219, a voltage controlled system clock 221, a ¼ frequency dividing circuit 222, a sounder DA converter 231, a sounder 230, a drive circuit Driver, a battery monitor AD converter 232, battery monitor circuit 233, a battery 234, a CPU RAM 239, a CPU ROM 238, an LCD (liquid crystal device and a liquid crystal panel) 237, a SIM (subscriber identity module) 236 and a keyboard 235. The baseband analog front end (AFE) 202 includes a PA (power amp) D/A converter 203, an I/Q AD/DA converter 204, an AGC (auto gain control) D/A converter 205, an audio AD/DA converter 206, and an AFC (auto frequency control) D/A converter 207. The DSP RAM (200) and the DSP ROM (201) are connected through an external DSP bus 240 to the DSP chip 223.
The function and operation of this terminal will be explained briefly.
During the audio transmission, the voice input from the microphone 208 is amplified by the amplifier Amp, and converted into digital data by being sampled at the audio A/D converter 206. The sampling rate is 8 kHz, and the bit accuracy is 13 bits. The data thus digitized is sent to the DSP chip 223, and after being compressed and encoded for the communication path, delivered to the I/Q D/A converter 204 of the analog front end (AFE) 202. This signal is modulated and converted into analog data and input to the RF modem 210. The resulting signal is sent out from the antenna 213 over an RF frequency (800 MHz). The duplexer (214) is used for separating the input radio wave from the output radio wave. The high-frequency sine wave 217 used for high-frequency modulation/demodulation is synthesized by a frequency synthesizer 216. The frequency synthesizer 216 is connected through a signal line 218 to the CPU chip 227. The ROM (201) has built therein a program executed by the DSP chip 223. The RAM (200) is used for operating the DSP chip 223.
At the time of audio receiving, the data received by the antenna 213 are input to the RF modem 210 through the low-noise amplifier (LNA) 215. This signal is converted into a low-frequency baseband analog signal, and is delivered to the I/Q A/D converter 204 of the analog front end (AFE) 202. The data sampled and converted into digital data are sent to the DSP chip 223 where it is demodulated, channel decoded and decompressed. After that, the data is converted into analog data at the audio D/A converter 206 and output from the speaker 209.
When the user makes a phone call, he uses a keyboard 235 and an LCD (237). The SIM 236 is a replaceable user ID module, which is mounted on the communication terminal to enable the user to use the terminal exclusively. The ROM (238) has built therein a program that can be executed by the CPU chip 227. The RAM (239) is used for operating the CPU chip 227. The battery 234 is a main battery for the whole terminal, and the remaining capacity of the battery 234 is monitored by the CPU chip 227 through the battery monitor circuit 233 and the battery monitor A/D converter 232. When there is a telephone call, the CPU chip 227 turns on the sounder 230 through the sounder D/A converter 231.
The basic clock 13 MHz of this terminal is supplied from the voltage controlled system clock 221. From this basic clock, the system timing circuit 219 produces required system timing signals 241, 220 and distribute them into the terminal. The basic clock is also supplied to the DSP chip 223 and the CPU chip 227. The DSP processing in the GSM is said to require 20 to 50 MIPS (mega instructions per second). In FIG. 2, the DSP chip operates at 52 MHz, i.e., a frequency four times as high as the basic clock 13 MHz using a PLL (phase locked loop) circuit 225 mounted in the DSP chip. The CPU processing in the GSM, on the other hand, is said to require 1 to 2 MIPS. In FIG. 2, therefore, a frequency one fourth the basic clock 13 MHz is generated by the ¼ frequency divider circuit 222, and the CPU is operated at this rate.
The basic clock 13 MHz of the terminal is required to be strictly synchronized with the master clock frequency 13 MHz of the base station. This is achieved in the manner described below. First, the strict frequency information is received from the base station. The DSP controls the voltage controlled system clock 221 through an AFC (automatic frequency control) D/A converter 207 on the basis of this information thereby to regulate the frequency. Also, an instruction for outputting a radio wave may be applied from the base station to the terminal. In that case, the DSP chip 223 drives the PA (power amplifier) D/A converter 203 and regulates the output of the power amplifier (PA) 212. Further, the DSP chip 223 regulates the gain of the RF modem through the AGC (automatic gain control) D/A converter 205 on the basis of the amplitude information of the received signal.
The communication between the DSP chip 223 and the CPU chip 227 is effected in the following manner. The DSP chip 223 is connected through a DSP host interface (HIF) 224 to a CPU external bus 229 of the CPU chip. The CPU chip 227 can freely read and write the internal resources of the DSP chip 223 from the DSP host interface (HIF) 224 through the CPU external bus interface 228 and the CPU external bus 229. When the DSP chip 223 is desirous of informing the CPU chip 227, an INT (interrupt) signal 226 is used.
The above-described conventional method using two independent units of DSP and CPU, however, requires two different memory systems for the DSP and the CPU. In the above-mentioned well-known system, all the DSP memories are formed on a chip. This is because that the GSM system has just introduced and the capacity required for the DSP memory is still small. In the case where the half-rate audio encoding technique is introduced in full scale with the increase in the number of subscribers in the future, however, the terminal is required to accommodate both the full-rate and the half-rate techniques. In that case, both of the speech encoding programs are required to be incorporated in the DSP. Further, since the current full-rate sound quality for the GSM system is not satisfactory, an enhanced full-rate audio encoding system is being studied. Once this system is realized, three speech encoding programs must be incorporated. Also, a DSP program for an added value such as a speech recognition program for voice dialing will probably be incorporated as a technique for differentiating the communication terminals. Therefore, it is not practicable, if only in terms of cost, to package as a chip all the DSP programs expected to increase in the future.
In the future, therefore, a memory external to the DSP seems unavoidable. In view of the fact that the reduction in cost, power consumption and size is crucial for a mobile communication terminal, however, the use of two external memories poses a great problem.
On the other hand, two systems of data input-output peripheral units have so far been required for DSP and CPU. This causes an extraneous communication overhead between the DSP and the CPU.